Atmel的AT86RF230是低功耗2.4GHz ZigBee/IEEE802.15.4 收發(fā)器,是真正的SPI到天線的解決方案.除了天線,晶體振蕩器和去耦電容外,所有的RF主要元件都集成在單一芯片內(nèi).

單片無(wú)線電收發(fā)器AT86RF230是在天線和微控制器接口間完整的無(wú)線電收發(fā)器.它包括了模擬無(wú)線電收發(fā)器和數(shù)字解調(diào)器,包括時(shí)間和頻率同步以及數(shù)據(jù)緩沖器.而雙向差分引腳用于RX和TX,因此不需要外部的天線開(kāi)關(guān).解決方案包括了AT86RF230的主要性能,方框圖以及應(yīng)用電路圖.

The AT86RF230 is a low-power 2.4 GHz transceiver specially designed for low cost ZigBee/IEEE802.15.4 applications. The AT86RF230 is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip. This single-chip radio transceiver provides a complete radio transceiver interface between the antenna and the microcontroller. It comprises the analog radio transceiver and digital demodulation including time and frequency synchronization and data buffering. The number of external components is minimized such that only an antenna, a crystal and four decoupling capacitors are required. The bidirectional differential antenna pins are used for RX and TX, so that no external antenna switch is needed.
The receiver path is based on a low-IF architecture. The channel filter consists of a single
sideband active RC resonator forming a 2 MHz band-pass filter with a Butterworth

characteristic centered at 2 MHz. Two 1st-order high-pass filters are added to the signal path to achieve capacitive coupling at the single side-band filter (SSBF) output to suppress DC offset at the limiter amplifier. The limiter amplifier provides sufficient gain to overcome the DC offset of the succeeding ADC and generates a digital RSSI signal with 3 dB granularity. The low-IF signal is sampled at 16 MHz and is applied to the baseband digital signal processor.

On the transmit side, direct VCO modulation is used. The modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding (spreading). This is equivalent to minimum shift keying (MSK) when transforming the spreading code sequences appropriately. The modulation signal is passed to the fractional-N PLL generating a coherent phase modulation required for O-QPSK demodulation. The frequency-modulated LO signal is fed to the power amplifier.

Two on-chip low-dropout (LDO) voltage regulators provide the internal analog and digital 1.8V supply. The SPI interface and the control registers retain their settings in SLEEP state (see section 7) when the regulators are turned off.

主要特性:

High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4 and ZigBee Applications
Industry Leading Link Budget (104 dB):
Programmable Output Power from -17 dBm up to 3 dBm
Receiver Sensitivity -101 dBm
Ultra-Low Power Consumption:
SLEEP: 0.1 μA
RX: 16 mA
TX: 17 mA (at max Transmit Power of 3 dBm)
Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator
Optimized for Low BoM Cost and Ease of Production:
Few External Components Necessary (Crystal, Capacitors and Antenna)
Excellent ESD Robustness
Easy to Use Interface:
Registers and Frame Buffer Accessible through Fast SPI
Only Two Microcontroller GPIO Lines Necessary
One Interrupt Pin from Radio Transceiver
Clock Output with Prescaler from Radio Transceiver
Radio Transceiver Features:
128-byte SRAM for Data Buffering
Programmable Clock Output, to Clock the Host Microcontroller or as Timer Reference
Integrated TX/RX Switch
Fully Integrated PLL with on-chip Loop Filter
Fast PLL Settling Time
Battery Monitor
Fast Power-Up Time < 1 ms
Special IEEE 802.15.4-2003 Hardware Support:
FCS Computation
Clear Channel Assessment
Energy Detection / RSSI Computation
Automatic CSMA-CA
Automatic Address Filtering
Automatic Acknowledge
Industrial Temperature Range:
-40° C to 85° C
I/O and Packages:
32-pin Low-Profile QFN
RoHS/Fully Green
Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210
Compliant to IEEE 802.15.4-2003

AT86RF230方框圖:

AT86RF230簡(jiǎn)化應(yīng)用電路圖:

AT86RF230評(píng)估板外形圖:

AT86RF230應(yīng)用電路圖:

詳情請(qǐng)見(jiàn)AT86RF230數(shù)據(jù)表:

>http:///dyn/resources/prod_documents/doc5131.pdf