1 多時(shí)鐘域的異步復(fù)位同步釋放

當(dāng)外部輸入的復(fù)位信號(hào)只有一個(gè)，但是時(shí)鐘域有多個(gè)時(shí)，使用每個(gè)時(shí)鐘搭建自己的復(fù)位同步器即可，如下所示。

verilog代碼如下：

module CLOCK_RESET( input rst_n, input aclk, input bclk, input cclk, output reg  arst_n, output reg  brst_n, output reg  crst_n );  reg arst_n0,arst_n1;reg brst_n0,brst_n1;reg crst_n0,crst_n1;  always @(posedge aclk or negedge rst_n)  if(rst_n==0) begin arst_n0<=1'b1; arst_n1<=1'b0; arst_n<=1'b0; end else begin arst_n<=arst_n1; arst_n1<=arst_n0; end  always @(posedge bclk or negedge rst_n)  if(rst_n==0) begin brst_n0<=1'b1; brst_n1<=1'b0; brst_n<=1'b0; end else begin brst_n<=brst_n1; brst_n1<=brst_n0; end   always @(posedge cclk or negedge rst_n)  if(rst_n==0) begin crst_n0<=1'b1; crst_n1<=1'b0; crst_n<=1'b0; end else begin crst_n<=crst_n1; crst_n1<=crst_n0; end   endmodule

RTL圖如下：

2 多時(shí)鐘域的按順序復(fù)位釋放

當(dāng)多個(gè)時(shí)鐘域之間對(duì)復(fù)位釋放的時(shí)間有順序要求時(shí)，將復(fù)位同步器級(jí)聯(lián)起來(lái)就可以構(gòu)成多個(gè)時(shí)鐘域按順序的復(fù)位釋放（實(shí)際上就是延遲兩拍）。

verilog代碼：

module CLOCK_RESET( input rst_n, input aclk, input bclk, input cclk, output reg  arst_n, output reg  brst_n, output reg  crst_n );  reg arst_n0,arst_n1;reg brst_n0,brst_n1;reg crst_n0,crst_n1;  always @(posedge aclk or negedge rst_n)  if(rst_n==0) begin arst_n0<=1'b1; arst_n1<=1'b0; arst_n<=1'b0; end else begin arst_n<=arst_n1; arst_n1<=arst_n0; end  always @(posedge bclk or negedge rst_n)  if(rst_n==0) begin brst_n1<=1'b0; brst_n<=1'b0; end else begin brst_n<=brst_n1; brst_n1<=arst_n; end   always @(posedge cclk or negedge rst_n)  if(rst_n==0) begin crst_n1<=1'b0; crst_n<=1'b0; end else begin crst_n<=crst_n1; crst_n1<=brst_n; end   endmodule 

RTL圖如下：