Xilinx FPGA程序升級詳解
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Xilixn FPGA提供了一種在線升級的方式，可以通過ICAP指令實(shí)現(xiàn)。ICAP(Internal Configuration Access Port) 指的是內(nèi)部配置訪問端口，其主要作用是通過內(nèi)部配置訪問端口（ICAP），用戶可以在FPGA邏輯代碼中直接讀寫FPGA內(nèi)部配置寄存器（類似SelectMAP），從而實(shí)現(xiàn)特定的配置功能，例如Multiboot。FPGA實(shí)現(xiàn)IPROG通常有兩種方式，一種是通過ICAP配置，一種是把相關(guān)指令嵌入bit文件中。與通過bit文件實(shí)現(xiàn)IPROG相比，通過ICAP更靈活。對Xilinx FPGA的升級其實(shí)是Multiboot的操作。如下圖所示，基地址存放的是Golden Image(bootloader)，而高地址存放的是MultiBoot Image。小編會在本文對Xilinx 7系列的MulTIboot做一些簡單介紹。
程序在啟動的過程中，首先會加載MultiBoot Image，然后判斷配置是否成功，這一步一般都是由外部電路決定，如果成功，則FPGA芯片上運(yùn)行的是MultiBoot Image，如果失敗，程序會自動返回到Golden Image。
1.STARTUP原語
我們都知道fpga掉電程序會丟失，一般使用外部flash存儲代碼，flash有spi、bpi、qspi等接口，外部存儲器的時鐘管腳一般與fpga的CCLK_0連接（BANK0），當(dāng)使用遠(yuǎn)程更新時，首先fpga內(nèi)部有控制flash的驅(qū)動（即邏輯控制flash時序）的時鐘，當(dāng)然flash時鐘也需要控制了，但這時時鐘管腳已經(jīng)連接到CCLK_0，這時候就需要用STARTUPE2(7系列)，SPANTAN系列使用STARTUPE原語，而UltraScale系列使用STARTUPE3原語，小編使用的是xc7k325的器件，所以：
STARTUPE2 #( .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation ) STARTUPE2_inst ( .CFGCLK(), // 1-bit output: Configuration main clock output .CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output .EOS(), // 1-bit output: Active high output signal indicating the End Of Startup. .PREQ(), // 1-bit output: PROGRAM request to fabric output .CLK(0), // 1-bit input: User start-up clock input .GSR(0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) .GTS(0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) .KEYCLEARB(1), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) .PACK(1), // 1-bit input: PROGRAM acknowledge input .USRCCLKO(flash_clk), // 1-bit input: User CCLK input**將SPI的時鐘鏈接到這里** .USRCCLKTS(0), // 1-bit input: User CCLK 3-state enable input .USRDONEO(1), // 1-bit input: User DONE pin output control .USRDONETS(1) // 1-bit input: User DONE 3-state enable outpu );
其中flash_clk就是時序控制的flash時鐘信號，連接到這就行了，其它的不需要改動，也無需約束此管腳（因?yàn)榧s束會報(bào)錯，小編已經(jīng)踩過坑了）。
其實(shí)在Xilinx上的Xilinx SPI Controller里面包含STARTUP原語，如下圖所示，所以對于Xilinx支持的FLASH芯片廠商如：Micron，Winbond，Spansion等，不需要再例化該原語。
SPI-controller
2.ICAP原語
IRPOG命令序列是實(shí)現(xiàn)FPGA重加載的重要環(huán)節(jié)。IPROG命令的效果與在PROGRAM_B引腳產(chǎn)生一個脈沖的效果類似，但是IPROG命令不對重配置[4]邏輯進(jìn)行復(fù)位。Kintex7內(nèi)部ICAPE2模塊能夠執(zhí)行IPROG命令，IPROG命令觸發(fā)FPGA從SPI Flash中重新加載比特文件，加載地址是Kintex7中WBSTAR寄存器指定的地址。
IPROG命令發(fā)送后，F(xiàn)PGA完成3個動作：
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發(fā)送同步字節(jié)（AA995566）；
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向Kintex7的WBSTAR寄存器寫入下一個加載地址(下表地址為00000000)；
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發(fā)送IPORG命令(0000000F)。
下表是通過ICAPE2向重配置模塊發(fā)送IPROG命令的順序。
ICAPE2編程命令程序?qū)崿F(xiàn)如下圖所示
ICAPE2 #( .DEVICE_ID(0'h3651093 ), // Specifies the pre-programmed Device ID value to be used for simulation .ICAP_WIDTH ("X32" ), // Specifies the input and output data width. .SIM_CFG_FILE_NAME ("C:\\VivadoPrj\\FPGAUartProgram\\7Serial\\7Serial_A7\\7Serial_A7.runs\\impl_1\\OnlineProgram_top.bit" ) // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation model. ) ICAPE2_inst ( .O (ICAPE2_O ), // 32-bit output: Configuration data output bus .CLK (ICAPE2_CLK ), // 1-bit input: Clock Input .CSIB (ICAPE2_CSIB ), // 1-bit input: Active-Low ICAP Enable .I (ICAPE2_I ), // 32-bit input: Configuration data input bus .RDWRB (ICAPE2_RDWRB ) // 1-bit input: Read/Write Select input );
注意有坑在這里哦
坑一：需要注意的是Flash的地址為24bit時候，需要將該Warm addr的高24位置為所需要的切換的鏡像地址。
坑二：需要對WBSTAR進(jìn)行字節(jié)內(nèi)交換
具體實(shí)現(xiàn)程序如下所示：
ICAPE2_I[0] <= icape2_data_r[7]; ICAPE2_I[1] <= icape2_data_r[6]; ICAPE2_I[2] <= icape2_data_r[5]; ICAPE2_I[3] <= icape2_data_r[4]; ICAPE2_I[4] <= icape2_data_r[3]; ICAPE2_I[5] <= icape2_data_r[2]; ICAPE2_I[6] <= icape2_data_r[1]; ICAPE2_I[7] <= icape2_data_r[0]; ICAPE2_I[8] <= icape2_data_r[15]; ICAPE2_I[9] <= icape2_data_r[14]; ICAPE2_I[10] <= icape2_data_r[13]; ICAPE2_I[11] <= icape2_data_r[12]; ICAPE2_I[12] <= icape2_data_r[11]; ICAPE2_I[13] <= icape2_data_r[10]; ICAPE2_I[14] <= icape2_data_r[9]; ICAPE2_I[15] <= icape2_data_r[8]; ICAPE2_I[16] <= icape2_data_r[23]; ICAPE2_I[17] <= icape2_data_r[22]; ICAPE2_I[18] <= icape2_data_r[21]; ICAPE2_I[19] <= icape2_data_r[20]; ICAPE2_I[20] <= icape2_data_r[19]; ICAPE2_I[21] <= icape2_data_r[18]; ICAPE2_I[22] <= icape2_data_r[17]; ICAPE2_I[23] <= icape2_data_r[16]; ICAPE2_I[24] <= icape2_data_r[31]; ICAPE2_I[25] <= icape2_data_r[30]; ICAPE2_I[26] <= icape2_data_r[29]; ICAPE2_I[27] <= icape2_data_r[28]; ICAPE2_I[28] <= icape2_data_r[27]; ICAPE2_I[29] <= icape2_data_r[26]; ICAPE2_I[30] <= icape2_data_r[25]; ICAPE2_I[31] <= icape2_data_r[24];
其實(shí)在Xilinx上的Block Design中也有ICAP的IP核，所以在進(jìn)行設(shè)計(jì)的時候也可以直接調(diào)用該IP進(jìn)行實(shí)現(xiàn)跳轉(zhuǎn)功能。
坑三：需要對外部SPI接口進(jìn)行約束
約束如下：
set cclk_delay 6.7 # Following are the SPI device parameters # Max Tco set tco_max 7 # Min Tco set tco_min 1 # Setup time requirement set tsu 2 # Hold time requirement set th 3 # Following are the board/trace delay numbers # Assumption is that all Data lines are matched set tdata_trace_delay_max 0.25 set tdata_trace_delay_min 0.25 set tclk_trace_delay_max 0.2 set tclk_trace_delay_min 0.2 ### End of user provided delay numbers # This is to ensure min routing delay from SCK generation to STARTUP input # User should change this value based on the results # Having more delay on this net reduces the Fmax # Following constraint should be commented when the STARTUP block is disabled set_max_delay 1.5 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO] -datapath_only set_min_delay 0.1 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO] # Following command creates a divide by 2 clock # It also takes into account the delay added by the STARTUP block to route the CCLK # This constraint is not needed when the STARTUP block is disabled # The following constraint should be commented when the STARTUP block is disabled create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_pins -hierarchical *USRCCLKO] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay] # Enable the following constraint when STARTUP block is disabled #create_generated_clock -name clk_virt -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports] -edges {3 5 7} # Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge # Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall; set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall; set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] # Data is captured into SPI on the following rising edge of SCK # Data is driven by the IP on alternate rising_edge of the ext_spi_clk set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO]; set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min -$th - $tclk_trace_delay_max] [get_ports IO*_IO]; set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
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