每個便攜設備或者手持設備工程師都知道使功耗最小化是當前設計絕對需要的。但是，一個經驗豐富的工程師就會明白微妙的細節(jié)可以使電池壽命延長到最大。這篇文章主要關注老練的專家怎樣使用極低功耗的CPLD從嵌入式設計的I/O子系統(tǒng)里去擠出一點功耗。

我們先回顧一下CPLD在嵌入式設計中一般被用來減少功耗和版大小，以及BOM成本。接下來，我們看怎樣在待機模式下減少CPLD功耗，不只是小心選擇設備，而且是選擇一個合適的總線結構。我們在工作狀態(tài)下的節(jié)能探索將包括選擇邏輯門技術，智能I/O設計技術及精確電壓供電管理技術。

Any engineer involved with portable or handheld products knows that minimizing power
consumption is an absolute requirement for today’s designs. But only the veterans
understand the subtle yet important details that can stretch a systems’ battery life to the
maximum. In this article we’ll focus on how those seasoned experts use ultra-low-power
complex programmable logic devices (CPLDs) to wring out every last microwatt from
the I/O subsystems of their embedded designs.

We'll begin by reviewing how CPLDs are commonly used to shrink power, board space and BOM costs in embedded designs. Next, we'll see how to minimize a CPLD's power consumption in its standby mode, not only by carefully selecting the device itself but also by choosing an appropriate bus parking scheme. Our exploration of power conservation during active operation will include techniques such as selective logic gating, smart I/O design and precision supply voltage management.

詳情請下載：lattice_practical_power.pdf