廉價(jià)的復(fù)合信號(hào)處理器消除了外部模擬電路。

　　將一個(gè)LVDT(線性可變差分變壓器)連接到微控制器是有挑戰(zhàn)性的工作，因?yàn)長(zhǎng)VDT需要交流輸入激勵(lì)和交流輸出的測(cè)量，以確定其可移動(dòng)核的位置(參考文獻(xiàn)1)。多數(shù)微控制器都缺乏專(zhuān)用交流信號(hào)生成與處理能力，因此需要外部電路產(chǎn)生任意諧波、波幅與穩(wěn)定頻率的正弦波信號(hào)。LVDT輸出信號(hào)的波幅與相位轉(zhuǎn)換成與微控制器內(nèi)部ADC兼容的形式，一般需要添加外部電路。

　　與傳統(tǒng)微控制器相比，Cypress半導(dǎo)體公司的PSoC微控制器含有用戶(hù)可配置的邏輯和模擬模塊，簡(jiǎn)化交流信號(hào)的生成與測(cè)量。PSoC器件具有無(wú)需連續(xù)CPU的干預(yù)就能生成模擬信號(hào)的獨(dú)特功能。PSoC靈活的模擬與數(shù)字模塊可以驅(qū)動(dòng)一支LVDT，并無(wú)需外部電路就可以測(cè)量其輸出。圖1顯示的是LVDT接口的完整電路，圖2顯示的是PSoC微控制器的內(nèi)部電路框圖。

圖1 LVDT接口的完整電路

圖2 PSoC微控制器的內(nèi)部電路框圖

　　PSoC采用多對(duì)用戶(hù)可配置的開(kāi)關(guān)電容器模塊，實(shí)現(xiàn)帶通和低通濾波器。通過(guò)生成方波，并通過(guò)建立在首個(gè)開(kāi)關(guān)電容器模塊中的穩(wěn)壓器，加在PSoC開(kāi)關(guān)電容濾波器上，從而創(chuàng)建

高質(zhì)量正弦波。通過(guò)一個(gè)中心位于方波基頻的窄帶帶通濾波器，方波可以去除絕大多數(shù)諧波。

　　為從PSoC開(kāi)關(guān)電容帶通濾波器產(chǎn)生最高保真度的正弦波，要使用盡可能高的過(guò)采樣速率，因數(shù)約為33，即每個(gè)正弦波周期33階。合成的正弦波足夠平滑到足以驅(qū)動(dòng)能衰減殘余更高諧波的LVDT。用可編程增益放大器調(diào)整PSoC的內(nèi)部電壓基準(zhǔn)，可以在濾波前對(duì)方波幅度作粗略的控制。為補(bǔ)償波形直流偏置電壓，放大器對(duì)2.6V內(nèi)部模擬地基準(zhǔn)進(jìn)行緩沖，并驅(qū)動(dòng)用作LVDT模擬地回路的輸出管腳。

　　LVDT輸出由幅度可變的正弦波電壓組成，其相對(duì)于正弦波激勵(lì)電壓的相位角要經(jīng)受一個(gè)相當(dāng)大的可變移位，有時(shí)相移會(huì)超過(guò)180。LVDT的信號(hào)驅(qū)動(dòng)PSoC的可編程增益放大器，其輸出送至開(kāi)關(guān)電容低通濾波器，跟隨一個(gè)用于同步整流的穩(wěn)壓器。整流后的信號(hào)驅(qū)動(dòng)一輸出管腳，以及PSoC的開(kāi)關(guān)電容ADC。

　　將LVDT輸出加在同步穩(wěn)壓器上，跟隨一個(gè)低通濾波器，產(chǎn)生直流電壓送至ADC或直接驅(qū)動(dòng)模擬反饋控制系統(tǒng)。在PSoC微控制器中，連接到ADC的低通開(kāi)關(guān)電容濾波器需要相同的采樣時(shí)鐘驅(qū)動(dòng)這兩個(gè)電路，導(dǎo)致PsoC的11位Δ-S ADC的轉(zhuǎn)換速率大約是低通濾波器角頻率的一半。同步穩(wěn)壓產(chǎn)生兩倍激勵(lì)頻率紋波頻率，因此更容易被低通濾波器去除。將、重新設(shè)計(jì)低通濾波器的角頻率為激勵(lì)頻率的三分之一，就可以在等于或低于1 LSB（最低有效位）標(biāo)準(zhǔn)差下，使LVDT輸出的測(cè)量達(dá)到11位分辨率。

　　用配置為計(jì)數(shù)器鏈的邏輯電路塊將PsoC的24MHz內(nèi)部系統(tǒng)時(shí)鐘分頻，產(chǎn)生開(kāi)關(guān)電容器模擬電路模塊所需的數(shù)字時(shí)鐘信號(hào)。在加電或復(fù)位后，PSoC的CPU配置所有可配置的模擬和數(shù)字電路模塊，并開(kāi)始運(yùn)行。從那以后，硬件便能夠激勵(lì)LVDT，并無(wú)需CPU參與的情況下，以每秒500次采樣速率測(cè)量其輸出。當(dāng)PSoC CPU運(yùn)行在12MHz時(shí)，處理ADC內(nèi)部動(dòng)作和中斷只消耗CPU不到3%的資源。

　　大量PSoC資源仍可用于計(jì)算LVDT位置，以及在LCD模塊上以文本形式顯示結(jié)果。四個(gè)模擬電路模塊、五個(gè)邏輯電路模塊和很多I/O管腳都可用于支持更高要求的應(yīng)用。圖3顯示了可用于附加功能的可配置模塊。

圖3 可用于附加功能的可配置模塊

　　參考文獻(xiàn)：

　　1、"Linear variable differential transformer，" Wikipedia

　　英文原文：

　　PSoC microcontroller and LVDT measure position

　　Low-cost mixed-signal processor eliminates external analog circuitry.

　　Sigurd Peterson, Sig3 Consulting, Aloha, OR; Edited by Brad Thompson and Fran Granville -- EDN, 10/26/2006

　　Connecting an LVDT (linear-variable-differential transformer) to a microcontroller can prove challenging because an LVDT requires ac-input excitation and measurement of ac outputs to determine its movable core's position (Reference 1). Most microcontrollers lack dedicated ac-signal-generation and -processing capabilities and thus require external circuitry to generate harmonic-free, amplitude- and frequency-stable sine-wave signals. Conversion of an LVDT's output signals' amplitude and phase into a form compatible with a microcontroller's internal ADC usually requires additional external circuitry.

　　In contrast with conventional microcontrollers, Cypress Semiconductor Corp's PSoC microcontrollers include user-configurable logic and analog blocks that simplify generation and measurement of ac signals. PSoC devices have the unusual feature of being able to generate analog signals without demanding continuous CPU attention. The PSoC's flexible analog and digital blocks can drive an LVDT and measure its outputs without requiring any external circuitry. Figure 1 shows the complete circuit of the LVDT interface, and Figure 2 shows the PSoC microcontroller's internal circuit blocks.

　　The PSoC uses pairs of user-configurable switched-capacitor blocks to implement both bandpass and lowpass filters. You can create a high-quality sine wave by generating a square wave and applying it to a PSoC switched-capacitor filter through a modulator built into the first switched-capacitor block. Passing the square wave through a narrow bandpass filter centered on the square wave's fundamental frequency removes most of the harmonics.

　　To obtain the highest fidelity sine waveform from a PSoC switched-capacitor bandpass filter, use the highest possible oversampling rate—a factor of approximately 33—or 33 steps per sine-wave cycle. The resultant sine wave is smooth enough to drive an LVDT, which attenuates any residual higher order harmonics. Scaling the PSoC's internal voltage reference with a programmable-gain amplifier provides coarse control over the square wave's amplitude before it undergoes filtering. To compensate for the waveform's dc-offset voltage, an amplifier buffers the 2.6V internal analog-ground reference and drives an output pin that serves as the LVDT's analog-ground return.

　　The LVDT's output consists of a variable-amplitude sine-wave voltage whose phase angle with respect to the sine-wave excitation voltage undergoes a significant and variable shift that sometimes exceeds 180°. A signal from the LVDT drives one of the PSoC's programmable-gain amplifiers, whose output feeds a switched-capacitor lowpass filter followed by a modulator for synchronous rectification. The rectified signal drives an output pin and o

ne of the PSoC's switched-capacitor ADCs.

　　Applying the LVDT's output to a synchronous rectifier followed by a lowpass filter produces a dc voltage that can feed an ADC or directly drive an analog feedback-control system. In a PSoC microcontroller, a lowpass switched-capacitor filter connected to an ADC requires that the same sample clock drive both circuits, resulting in a conversion rate for the PSoC's 11-bit delta-sigma ADC that's approximately one-half of the lowpass filter's corner frequency. Synchronous rectification produces a ripple frequency twice that of the excitation frequency and thus is easier to remove with a lowpass filter. Relocating the lowpass filter's corner frequency to one-third of the excitation frequency allows measurements of the LVDT's output to 11-bit resolution with a standard deviation of 1 LSB (least significant bit) or less.

　　Dividing the PSoC's 24-MHz internal system clock with logic blocks configured as counter chains generates all of the digital clock signals the switched-capacitor analog-circuit blocks require. After power application or a reset, the PSoC's CPU configures all the configured analog and digital blocks and starts their operation. From then on, the hardware excites the LVDT and measures its output at 500 samples/sec without further intervention by the CPU. With the PSoC's CPU running at 12 MHz, processing the ADC's housekeeping activities and interrupts consumes less than 3% of the CPU's resources.

　　Plenty of the PSoC's resources remain available for calculating the LVDT's position and for displaying the results in text format on an LCD module. Four analog blocks, five logic blocks, and many I/O pins remain available to support a more demanding application. Figure 3 shows configurable blocks that are available for adding features.

　　英文原文地址：http://www.edn.com/article/CA6382647.html