#include

#include

volatile unsigned int i = 0; // 中斷服務(wù)子程序中所用到的全局變量, 最好定義成 volatile 型, 具體原因和用法可以參考我的其他博文介紹

void main (void)

{

WDTCTL = WDT_MDLY_0_5; // 周期 0.5ms, 設(shè)置可參考下面頭文件中的截段

IE1 |= WDTIE; // 使能WDT中斷

P2DIR |= BIT2; // P2.2輸出

_EINT(); // 使能全局中斷

for (;;)

{

LPM0; // 進(jìn)入LPM0

_NOP();

}

}

// 看門狗中斷服務(wù)子程序

#pragma vector=WDT_VECTOR

__interrupt void WDT_Timer_ISR(void)

{

if (i++ > 1) {

P2OUT ^= BIT2; // 取反

}

}

//==========================================================================================================================

// 相關(guān)頭文件中的定義

/************************************************************

* WATCHDOG TIMER

************************************************************/

#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */

#define WDTCTL_ (0x0120u) /* Watchdog Timer Control */

DEFW( WDTCTL , WDTCTL_)

/* The bit names have been prefixed with "WDT" */

#define WDTIS0 (0x0001u)

#define WDTIS1 (0x0002u)

#define WDTSSEL (0x0004u)

#define WDTCNTCL (0x0008u)

#define WDTTMSEL (0x0010u)

#define WDTNMI (0x0020u)

#define WDTNMIES (0x0040u)

#define WDTHOLD (0x0080u)

#define WDTPW (0x5A00u)

/* WDT-interval times [1ms] coded with Bits 0-2 */

/* WDT is clocked by fSMCLK (assumed 1MHz) */

#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */

#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */

#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */

#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */

/* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */

#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */

#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */

#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */

/* Watchdog mode -> reset after expired time */

/* WDT is clocked by fSMCLK (assumed 1MHz) */

#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */

#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */

#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */

#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */

/* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */

#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */

#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */

#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */