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[導(dǎo)讀]1. S3C2440A has130multi-functional input/output port pins and there areeight portsas shown below:— Port A(GPA): 25-output port (output only)— Port B(GPB): 11-input/out port— Port C(GPC): 16-input/o

1. S3C2440A has130multi-functional input/output port pins and there areeight portsas shown below:

— Port A(GPA): 25-output port (output only)
— Port B(GPB): 11-input/out port
— Port C(GPC): 16-input/output port
— Port D(GPD): 16-input/output port
— Port E(GPE): 16-input/output port
— Port F(GPF): 8-input/output port
— Port G(GPG): 16-input/output port
— Port H(GPH): 9-input/output port
— Port J(GPJ): 13-input/output port

2. Port_Init:

//CAUTION:Follow the configuration order for setting the ports.
// 1) setting value(GPnDAT)

GPnDAT When the port is configured as output port, the pin state is the same as the corresponding bit.
When the port is configured asfunctional pin, theundefinedvalue will beread.

So rGPADAT undefined
// 2) setting control register (GPnCON)
// 3) configure pull-up resistor(GPnUP)

PORT A GROUP:

Register Address R/W DescriptionReset Value
GPACON 0x56000000 R/W Configures the pins of port A0xffffff
GPADAT 0x56000004R/W The data register for port A Undef.

//Ports : GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
//Signal : nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
//Binary : 1 1 1 , 1 11 1 , 1 1 1 1
//Ports : GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4GPA3 GPA2GPA1GPA0
//Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
//Binary : 1 1 1 1 , 1 1 1 1 , 1 1 1 1
rGPACON = 0x7fffff; //GPA0~GPA22 =0:output; =1:fuctionul.
注: 該處GPA0~GPA22都為1,選擇第二組功能:
ADDR0~ADDR26:ADDR[26:0] (Address Bus) outputs the memory address of the correspondingbank .
nGCS[7:0] :(General Chip Select) are activated when the address of a memory is within the address region of each bank. The number of access cycles and the bank size can be programmed.
nFCE : Nand flash chip enable
nFRE :Nand flash read enable
nFWE:Nand flash write enable
CLE : Command latch enable ALE : Address latch enable nRSTOUT : For external device reset control (nRSTOUT = nRESET & nWDTRST &SW_RESET)

PORT B GROUP
//Ports : GPB10GPB9 GPB8 GPB7 GPB6GPB5 GPB4 GPB3 GPB2GPB1 GPB0
//Signal :nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nXBREQ nXBACK TCLK0 TOUT3 TOUT2 TOUT1 TOUT0
//Setting: INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT OUTPUTOUTPUT OUTPUT OUTPUT OUTPUT
//Binary : 00 , 00 01 , 01 01 , 01 01 , 01 01 , 00 00
//rGPBCON = 0x000150;(youlong)
rGPBCON = 0x015550; //GPB0~GPB10:=00:INPUT=01:OUTPUT=10:fuctionul.
rGPBUP = 0x7ff; // The pull up function is disabled GPB[10:0] (0:enable 1:disable). 上拉全關(guān)
注: PB0:TOUT0 is a PWM output.(板上接著蜂鳴器)
PB1:
PB2:L3MODE接到音頻IC UDA1341第13腳
PB3:L3DATA接到音頻IC UDA1341第15腳
PB4:L3CLOCK 接到音頻IC UDA1341第14腳
PB5~PB8:LED1~LED4
PB9:
PB10:

PORT C GROUP

//Ports: GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8
//Signal :VD7VD6VD5 VD4VD3VD2VD1VD0
//Binary : 10 10 , 10 10 , 10 10 , 10 01 ,

//Ports: GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
//Signal : LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
//Binary : 01 01 , 01 10 , 10 10 , 10 10
rGPCCON = 0xaaa956aa; //00=INPUT 01=OUTPUT 10=fuctionul
rGPCUP = 0xffff; // The pull up function is disabled GPC[15:0]
注: 整個PC口都用在LCD控制上

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