[導讀]芯片設計之CDC異步電路(四)芯片設計之CDC異步電路(三)芯片設計之CDC異步電路(二)芯片設計之CDC異步電路(一)1?????CDC常見錯誤1.1?????Reconvergence1.1.1??????single_source_reconvergence結(jié)構(gòu)：同一個信號...
芯片設計之CDC異步電路(四)
芯片設計之CDC異步電路(三)
芯片設計之CDC異步電路(二)
芯片設計之CDC異步電路(一)
1?????CDC常見錯誤
1.1?????Reconvergence
1.1.1??????single_source_reconvergence
結(jié)構(gòu)：同一個信號源頭，兩個同步處理器。這里提一下，有兩個CDC分析工具的參數(shù)配置：1.1.2???????案列1：divergence_depths為0
// divergence pointalways @ (posedge tx_clk) ctrl <= ci0 | ci1 ; // two_dff synchronizeralways @ (posedge rx_clk) begin: two_dff reg temp; temp <= ctrl; two_dff_sync <= temp;end // shift_reg synchronizeralways @ (posedge rx_clk) begin: shift_reg shift_reg_sync <= {shift_reg_sync[0], ctrl};end // reconvergence pointalways @ (posedge rx_clk) dout <= two_dff_sync ^ shift_reg_sync[1]; 電路如下：divergence_depth為0CDC報告如下：
1.2?????Redundant案例1：
// two_dff synchronizer of tx_sigalways @ (posedge rx_clk) begin: two_dff reg s0 , s1; s0 <= tx_sig; // 1st flop s1 <= s0; // 2nd flopend
// two_dff synchronizer of tx_sigalways @ (posedge rx_clk) begin: shift_reg reg [1:0] sh_reg; sh_reg?<=?{sh_reg[0],?tx_sig};end??
1.3?????multi_sync_mux_select (DMUX)
MUX的sel端fan-in信號超過一組同步器，不推薦。通常MUX的sel端只能有一組同步器。案例1：
always @(posedge rx_clk) begin reg s1_sel1, s2_sel1; reg [1:0] s_sel2; s1_sel1 <= tx_sel1; s2_sel1 <= s1_sel1; s_sel2 <= {s_sel2[0], tx_sel2}; if (s_sel2[1] | s2_sel1)????????rx_data?<=?tx_data;end?電路如下：1.4?????combo_logic
1.4.1?????錯誤案列1
always @ (posedge rx_clk) begin s1 <= tx_sig 
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